OPA656 is a broadband, unity gain stable, field-effect transistor input operational amplifier 10

The total output DC bias voltage under any configuration and temperature will be a combination of multiple possible error terms. In JFET parts like OPA656, the input bias current term is usually low but not matching. The use of bias current cancellation technology is more typical in bipolar input amplifiers and does not improve the output DC bias error. The error caused by input bias current only becomes dominant at high temperatures. diode OPA656 shows a typical 2x increase in JFET input stage amplifier every 10 ° C. The maximum test value of 5pA at 25 ° C and internal self heating at 20 ° C (see thermal analysis) will result in a maximum input bias current of 5pA • 2 (105-25)/10=1280pA at 85 ° C. For non vertical configurations, this term is only applicable to input bias voltages with source impedance>750k Ω. This will also be the feedback resistance value for transient applications (see Figure 3), where the output DC error caused by the input bias current of the inverter is in order of contribution to the input bias voltage. Generally speaking, except for these extremely high impedance values, the output DC error caused by input bias current can be ignored.diode

The term that has the greatest impact on the output bias voltage after the input bias voltage itself is the PSRR of the negative power supply. This term is modeled as the input bias voltage offset caused by changes in negative power supply voltage (and+PSRR). The high-level test limit for PSRR is 62dB. This translates to a 1.59mV/V input bias voltage shift of 10 (-62/20). In the worst case, a deviation of ± 0.38V (± 7.6%) from the negative power supply voltage will result in a deviation of ± 0.6mV from the input bias voltage. Due to this being equivalent to the test limit of ± 0.6mV input bias voltage, careful control of the negative power supply voltage is required. +PSRR test to a minimum value of 74dB. This translates to a sensitivity of 10 (-74/20)=0.2mV/V to changes in the input bias voltage of the positive power supply.diode

For example, calculate the worst-case output DC error of the transient circuit at 25 ° C in Figure 1, and then provide the following assumptions for the offset in the range of 0 ° C to 70 ° C.

Negative power supply