How to Design with Capacitive Digital Isolators 4

Place the power layer beneath the ground layer. These two reference layers form an additional high-frequency bypass capacitor of approximately 100pF/in².

Route low-speed control signals at the bottom layer. These signal traces have sufficient margin to withstand interruptions caused by vias, thereby achieving greater flexibility.

A controlled impedance transmission line is a trace whose characteristic impedance Z0 is always governed by its geometric properties. When the trace length exceeds 15mm (tr=1ns) or 30mm (tr=2ns), the trace impedance must match the isolator's output impedance Z0~rO (as shown in Figure 4) to minimize signal reflection. This is referred to as source impedance matching.  diode

Figure 4 Source Impedance Matching: Z0 ~ rO

The dynamic output impedance r0 of the isolator can be obtained from the linear portion of the approximate voltage-current output characteristics listed in the isolator datasheet. Generally, the standard output impedance is approximately 70Ω. Therefore, for a standard 2-ounce copper-clad line and FR-4 with a dielectric constant of 4.5, a trace geometry of 8mm wide and 10mm long on the ground plane will yield the desired 70Ω characteristic impedance.

Cabling Guide

It is recommended to adhere to the following key wiring principles to ensure signal integrity and minimize EMI.

To reduce crosstalk below 10%, the signal trace must maintain a distance three times that between the high-speed signal layer and the ground layer (d=3h). The return current density beneath the signal trace follows the function 1/[1+(d/h)²], resulting in very low density at points where d>3h, thereby preventing significant crosstalk in adjacent traces (see Figure 5). diode