Application of FPGA in Intelligent Pressure Sensor Systems 5

The A/D converter AD1 in the system adopts an independent working mode, and its control pins are set to: CE and 12/8 are connected to high level; Connect CS and A0 to a low level. At this point, AD1 is set to 12 bit A/D conversion, with 12 bit data output, and its conversion is completely controlled by R/C, as shown in Figure 2. When R/C=O, initiate 12 bit A/D conversion; When the A/D conversion is completed, the status signal STS=0, otherwise STS=1; When R/C=1, read 12 bit A/D conversion data. The R/C signal is controlled by DAS-RC of the FPGA chip. The entire system is controlled by an FPGA based System on Chip (SoC). Among them, the DAS-STS, DAS-RC, DAS-IN, and DAS-A pins in the FPGA chip are user customized logic, which is the external interface of the DAS control unit, used to control the timing conversion of AD1 and the channel selection of AD7502. diode

3.1 Implementation of SoC Structure  diode

The SoPC design consists of components such as CPU, memory interface, standard peripherals, and user-defined logic unit modules. Altera's SoPCBuilder tool provides a large number of IP cores available for calling, making it easy to configure embedded Noise II processor cores, on-chip RAM and RS232 controllers, extended off chip memory, user customized logic units on a single FPGA chip. At the same time, it automatically assigns addresses to each external device of the system, connects to the system bus, and determines device priority. Its internal structure is shown in Figure 3.diode